1. Field of the Invention
The present invention relates to a stacked type semiconductor device.
2. Description of the Related Art
In response to an increase in storage capacity required for memory cards and the like, stacked type semiconductor devices (multichip devices) have been proposed which have semiconductor integrated circuit chips (LSI chips) stacked together. The stacked type semiconductor device has a plurality of chips stacked in a vertical direction. Accordingly, this device may be smaller in size (area) than that having chips arranged in a horizontal direction.
In the stacked type semiconductor device, the chips are electrically connected together via, for example, through plugs that penetrate the chips. Thus, to select a desired one of the stacked memory chips of the same structure, the chips must have chip enable bar (/CE) terminals arranged at different positions and which are used to activate (enable) the chip. This prevents the chips from having a common structure, thereby increasing manufacture costs.
To solve this problem, a method has been proposed wherein the chip enable bar terminals for chip selection or terminals to which chip address signals are input are arranged at the same positions of the chips by varying arrangement patterns of bumps used to connect the through plugs in the chips (U.S. Pat. No. 6,239,495). This proposal will be described with reference to FIG. 10.
Chips C1 to C4 are provided with through plugs PG connected together by bumps BP. In the figure, P1 denotes a terminal part to which chip address signals (CA0, CA1) used to select (activate) the desired chip are supplied. P2 denotes a part in which terminals used to specify a chip are formed and in which the bumps BP are arranged in a pattern varying among the chips C1 to C4. That is, in the chip C1, all three through plugs PG are connected to a ground potential (Vss). In the chip C2, two through plugs PG are connected to the ground potential (Vss). In the chip C3, one through plug PG is connected to the ground potential (Vss). In the chip C4, no through plugs PG are connected to the ground potential (Vss).
In this manner, the terminals for the chip address signals CA0, CA1 can be arranged at the same positions of the chips by varying the arrangement of the bumps BP and thus the connective relationship among the chips C1 to C4. Then, the desired chip can be selected using the chip address signals (CA0, CA1), by providing each of the chips C1 to C4 with a logic circuit that receives logic values from the terminals (through plugs PG) arranged in the areas denoted by P1 and P2.
However, the above described conventional technique allows the use of chips of the same structure but requires that the arrangement pattern of the bumps is varied among the chips. This hinders a common manufacture process from being appropriately used, thereby increasing manufacture costs. Further, the number of chip specifying terminals arranged in the area denoted by P2 in FIG. 10 increases consistently with the number of chips stacked together.
As described above, the conventional stacked type semiconductor device allows an arbitrary chip to be selected by varying the arrangement pattern of the bumps. This hinders a common manufacturing process from being appropriately used, thereby increasing manufacture costs. Further, the number of chip specifying terminals increases with the number of chips stacked together. Accordingly, it is desirable to provide a stacked type semiconductor device that can prevent an increase in manufacture costs or number of terminals.